1. Field of the invention
The present invention relates to a xe2x80x9csemiconductor device with a trench, the inner wall of which is covered with a dielectric material and which intends to reduce the capacitance, and a method for fabricating the same.
2. Description of the Related Art
Conventionally, a trench is used as a gate of a vertical MOS transistor such as a power MOSFET.
The trench has two types of structures, i.e. a V (shape)-trench and a U (shape)-trench. For example, as for the former, JP-A-55-48968 mainly relates to a horizontal MOS transistor, but discloses, (refer to FIG. 14 of the JP-A-55-48968), a vertical MOS transistor including a source region(21) formed around a V-trench gate and a drain region(26) of Nxe2x88x92 type layer disposed at a bottom of the V-trench, namely discloses a V-trench MOS transistor. On the other hand, the latter is disclosed in detail in JP-A-7-326741 and JP-A-7-263692.
For example, in the vertical MOS transistor disclosed in JP-A-7-263692, as shown in FIG. 12 of this application, an Nxe2x88x92 type semiconductor layer 10 is located on a N+ type semiconductor substrate (not shown) and a P type semiconductor layer 11 is formed on the Nxe2x88x92 type semiconductor layer 10. A trench 12 is formed from the surface of the semiconductor layer 11 so that the bottom and its vicinity is engaged in the Nxe2x88x92 type semiconductor layer 10.
The inner wall of the trench 12 is covered with a gate insulating layer 13. A conductive material such as polycrystalline silicon (poly-si) 14 is embedded in the trench 12. An N+ type source region 15 is formed around the trench 12. A source electrode 17 is formed through the source region 15 and an insulating film 16 surrounded by the source region 15 and formed to expose the surface of the Pxe2x88x92 type semiconductor layer.
The surface of the semiconductor layer outside the trench 12 between the source region 15 and the drain region 10 is inverted from P type into N type to form a channel so that a current flows from the source region 15 toward the drain side.
In (FIG. 14 of) JP-A-48968, a xe2x80x9cV-MOSxe2x80x9d, having a trench of V-shape is shown. In the V-MOSxe2x80x9d, an electric field is concentrated into the bottom so that breakage is likely to occur between the gate and drain. In addition, dry etching is difficult to carry out for machining and hence wet etching is commonly adopted. Therefore, the slanting angle of the V-trench is defined according to a crystal face so that the size of the opening cannot be increased. Further, owing to variations in the depth of the trench, Cgd varies greatly. This leads to variations in the switching speed.
On the other hand, the xe2x80x9cU-trenchxe2x80x9d of the MOS transistor disclosed in JP-A-7-263692 is machined by dry etching and draws xe2x80x9cRoundxe2x80x9d shape on the bottom. Therefore, unlike the V-trench, an electric field is prevented from being concentrated at the bottom. The capacitance Crss=Cgd between a trench bottom and Nxe2x88x92 type layer, however, is increased, thus retarding the switching speed.
Further, JP-A-7-326741 intends to remove a LOCOS to form a trench, (as shown in its FIG. 2). However, because the oxidizing step is required, the depth of the trench cannot be increased. In addition, owing to the formation of a bird""s beak, defects are likely to occur below the bird""s beak. When the LOCOS is grown to a deep position in order to increase the channel length, a long oxidizing time is required. Correspondingly, a bird""s beak is further grown, and the size of the opening of the trench is increased, thus increasing the capacitance. Further, the cell density cannot be increased and reduction of the on-resistance is difficult.
The present invention intends to solve these problems, particularly to reduce the capacitance and to realize high speed switching while preventing reduction of the cell density.
Assuming that the switching time of the transistor is T, Txe2x88x9dxcex1 (Cgs+Cgd). Cgs represents a gate-source capacitance. Since the source electrode is in contact with the P+ type semiconductor layer, it also represents the capacitance between the channel region and gate electrode. Cgd represents a gate-drain capacitance.
The present invention intends to reduce the capacitance to improve the switching characteristic.
The present invention has been accomplished in view of the problem described above, and first, intends to solve the problem in such a manner that the inner wall of the trench extending from a bottom of the trench to the surface of the semiconductor layer has a slope, and an angle of a tangent line of the slope formed with the surface of the semiconductor layer decreases constantly from the vicinity of a lower end of the channel region toward the surface of the semiconductor layer.
As shown in FIG. 11, if angles of a tangent line of the slope for the surface of a semiconductor substrate, xcex11, . . . xcex1n . . . are decreased toward the surface of the semiconductor substrate, the trench can have a sectional shape which is convex toward the inside of the trench. Further, the circumferential length of slope shaped trench as shown in FIG. 14B is small in comparison with that of the conventional rectangular type trench as shown in FIG. 14A. Namely a slope can be formed to reduce the circumferential length of the trench. The structure of the trench according to the present invention is referred to as xe2x80x9cxcex3 trenchxe2x80x9d in view of similarity of the shape.
A first aspect of the device is a semiconductor device of the present invention, which comprises:
a trench formed in a semiconductor layer of a first conduction type;
a gate oxide layer formed on an inner wall of said trench;
a gate conductor material embedded in said trench covered with the gate oxide layer; and
a channel region formed in a boundary of said semiconductor layer with said gate oxide layer,
wherein the inner wall of the trench extending from the bottom of said trench to the surface of the semiconductor layer has a slope, and an angle of a tangent line of said slope formed with the surface of said semiconductor layer decreases constantly from the vicinity of a lower end of said channel region toward the surface of said semiconductor layer.
As cell density is higher, although on-resistance is generally decreased, capacitance is increased. Contrary that, according to this device structure, capacitance can be decreased, even if the cell density is same as that of the conventional structure and thereby on-resistance remains the same as the conventional structure.
A second aspect of the device is a semiconductor device according to the first aspect, wherein said semiconductor layer is a first semiconductor layer of a first conduction type and said semiconductor device further comprises:
a source region formed on a surface of said first semiconductor layer;
a drain region of a second semiconductor layer of an opposite conduction type formed on a rear surface of said first semiconductor layer.
A third aspect of the method is a method of fabricating a semiconductor device and intends to solve the problem in such a manner of making etching with anisotropy stronger in a vertical direction with a deposit applied on a side wall to form the trench having a shape such that an angle of a tangent line of the slope formed with the surface of the semiconductor layer decreases constantly from the vicinity of a lower end of the channel region toward the surface of the semiconductor layer. This makes the etching speed in a vertical direction higher than in a horizontal direction, thereby completing the xcex3 trench. According to the method, adding to the effect according to the device above described, owing to the existence of the deposit applied on the side wall of the trench, without changing an opening width, capacitance can be reduced even in the conventional design scale as shown in FIG. 22.
A fourth aspect of the method is a method of fabricating a semiconductor device, intends to solve the problem in such a manner that an area of the trench, when it is cut horizontally, has an increasing rate from the lower end of the channel region toward the surface of the semiconductor substrate and a substantially zero increasing rate in the vertical vicinity of the lower end of the channel region. Thus, even if the depth of the trench varies, a variation of Cgd at the portion with the area increasing rate of substantially zero can be minimized.
A fifth aspect of the method is a method of fabricating a semiconductor device, and intends to solve the problem in such a manner that assuming that a vertical section of the trench has a length OP of an opening, a depth D1, a width BT2 of a bottom and a length D2 of a sloping line connecting the edge of the opening to that of the bottom, a dimension relationship: 2xc3x97D2+BT2 less than 2xc3x97D1+OP is set.
A sixth aspect of the device is a semiconductor device, and intends to solve the problem in such a manner that the inner wall of the trench extending from a bottom of the trench from the surface of the semiconductor layer has a slope, and an angle of a tangent line of the slope formed with the surface of the semiconductor layer decreases constantly from the vicinity of a lower end of the channel region toward the surface of the semiconductor layer.
As described above, the trench has a section of xcex3 shape, has a grid pattern in its planar shape. The trench has a structure in which the circumferential shape as shown in FIG. 14B is continuous vertically to the paper face. As compared with the U trench as shown in FIG. 14A, the circumferential length of the slope shaped trench can be reduced to decrease the resultant capacitance. This improves the switching speed of the vertical MOS transistor. By making the trench convex toward the inside thereof, BT2 of the bottom can be made smaller than the shape as shown in FIG. 14B, thereby decreasing the resultant capacitance C (GD)=Crss.
A seventh aspect of the device is a semiconductor device, and intends to solve the problem in such a manner that an area of the trench, when it is cut horizontally, has an increasing rate from the lower end of the channel region toward the surface of the semiconductor substrate and a substantially zero increasing rate in the vertical vicinity of the lower end of the channel region. Even if there is a certain variation of the depth of the trench, a variation of the surface area of the trench overlapping the drain region can be suppressed. Therefore, the capacitance C (GD)=Crss generating at the bottom of the trench can be made small with a slight variation.
An eighth aspect of the device is a semiconductor device, and intends to solve the problem in such a manner that assuming that a vertical section of the trench has a length of an opening of OP, a depth of D1, a width of a bottom of BT2 and a length of a line connecting the edge of the opening to that of the bottom, a relationship 2xc3x97D2+BT2 less than 2xc3x97D1+OP is set.
A ninth aspect of the device is a semiconductor device, and intends to solve the problem in such a manner that a bottom of the trench overlaps the vicinity of the surface of the second layer. According to the structure, by being able to reduce an overlapped area between the bottom of the trench and the second layer, Cgd can be reduced and therefore Crss can be reduced.
A tenth aspect of the device is a semiconductor device, and intends to solve the problem in a vertical type MOS semiconductor device in such a manner that the trench has a sectional shape having a dimension relationship: D2 less than D1+(OPxe2x88x92BT2)/2 where OP: a length of an opening of the trench,
D1: a depth of the trench,
D2: a length of a sloping line connecting the edge of the opening to that of a bottom of the trench,
BT2: a length of the bottom.
This aspect is based on the fact that the length of hypotenuse (one side) of a right triangle is smaller that the total of the remaining two sides. Specifically, by cutting both ends of the U trench to leave an area of a triangle indicated by arrows, a circumferential length can be shortened necessarily.
An eleventh aspect of the device is a semiconductor device, and intends to solve the problem in a vertical type MOS semiconductor device having a trench formed in a semiconductor layer and embedded with a gate material through a gate oxide layer on the inner surface of the trench, a source region (or drain region) formed on the periphery of an opening of the trench and a drain region (or source region) formed in the vicinity of a bottom of the trench, in such a manner that the trench has a slope which is convex toward above from a line connecting point S, which is a crossing point of the bottom of the source region (or drain region) and the trench, to point d, which is a lower end of a channel region formed in a boundary of the semiconductor layer with the gate insulating layer, and is substantially vertical (Refer to FIG. 24) in the vertical vicinity of the lower end of the channel region. According to this structure, channel length can be lengthened and thereby a breakdown voltage between source and drain is improved.
A twelfth aspect of the device is a semiconductor device, and intends to solve the problem in such a manner that the bottom of the trench has a prescribed width. According to this structure, concentration of the electric field, caused in the vicinity of the bottom of the trench, is prevented.
A thirteenth aspect of the device is a semiconductor device, and intends to solve the problem in such a manner that the MOS semiconductor device is a power MOS transistor.
A fourteenth aspect of the device is a semiconductor device, and intends to solve the problem in such a manner that the MOS semiconductor device is an IGBT (Insulating Gate typed Bipolar Transistor). IGBT has a structure similar to the power MOS, and the difference is only the conduction type of the substrate.
A fifteenth aspect of the method is a method of fabricating a semiconductor device, and intends to solve the problem in such a manner that the trench is etched using HBr as a main etching gas(a first effective species).
A sixteenth aspect of the method is a method of fabricating a semiconductor device, and intends to solve the problem in such a manner that the trench is made using a main etching gas of HBr mixed with He, O2 and N2 and at an adjustable etching rate.
A seventeenth aspect of the method is a method of fabricating a semiconductor device, and intends to solve the problem in such a manner of forming a film having resistance to dry etching on a surface of a semiconductor layer;
making an opening in the film to expose a region of the semiconductor layer corresponding to a trench to be formed; and
etching the region of the semiconductor layer corresponding to the opening using HBr as a main etching gas at a substantially uniform etching rate in a depth direction of the trench and a decreasing reduction rate of the width of the bottom according an increasing depth of the trench.